틀:List:CpuTechnology
| Architecture | Von Neumann, Harvard (Modified Harvard), Dataflow, TTA |
| Instruction set | ASIP, CISC, RISC, EDGE, EPIC, MISC, OISC, VLIW, NISC, ZISC, TRIPS, Comparison |
| Word size | 1-bit, 4-bit, 8-bit, 9-bit, 10-bit, 12-bit, 15-bit, 16-bit, 18-bit, 22-bit, 24-bit, 25-bit, 26-bit, 27-bit, 31-bit, 32-bit, 33-bit, 34-bit, 36-bit, 39-bit, 40-bit, 48-bit, 50-bit, 60-bit, 64-bit, 128-bit, 256-bit, 512-bit, variable |
| Execution | Instruction pipelining (Bubble * Operand forwarding), Out-of-order execution (Register renaming), Speculative execution (Branch predictor * Memory dependence prediction), Hazards |
| Parallel level | Bit (Bit-serial * Word), Instruction (Scalar * Superscalar), Task (Thread * Process), Data (Vector), Memory |
| Multithreading | Temporal, Simultaneous, Preemptive, Cooperative |
| Flynn's taxonomy | SISD, SIMD, MISD, MIMD (SPMD), Addressing mode |
| Types | Digital signal processor (DSP), GPGPU, Microcontroller (MCU), Physics processing unit, System on a chip (SoC), Cellular |
| Components | Address generation unit (AGU), Arithmetic logic unit (ALU), Barrel shifter, Floating-point unit (FPU), Back-side bus (Multiplexer * Demultiplexer), Registers, Memory management unit (MMU), Translation lookaside buffer (TLB), Cache, Register file, Microcode, Control unit, Clock rate |
| Power management | APM, ACPI, Dynamic frequency scaling, Dynamic voltage scaling, Clock gating |
| CPU hardware security | NX bit, Hardware restriction (firmware), Trusted Execution Technology, Secure cryptoprocessor, Hardware security module, Hengzhi chip |